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Verilog Hdl: A Guide To Digital Design And Synthesis

Verilog Hdl: A Guide To Digital Design And Synthesis

          
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About the Book

Written for both experienced and new users, this book gives you a broad coverage of Verilog HDL. The book stresses the practical design perspective of Verilog rather than emphasizing only the language aspects. The Information presented is fully compliant with the upcoming IEEE 1364 Verilog HDL standard.

Features

Provides full coverage of gate, dataflow (RTL), behavioral and switch level modeling
Introduces you to the Programming Language Interface (PLI)
Describes logic synthesis methodologies
Explains timing and delay simulation
Discusses ser-defined primitives
Offers practical modeling techniques and tips
Includes over 300 Illustrations, examples, and exercises, and a Verilog Internet reference resource list. Learning objectives and summaries are provided for each chapter. The CD-ROM contains a Verlog simulator with a graphical user interface and the source code for the examples in the book.

Contents

PART-I BASIC VERILOG TOPICS

Overview of Digital Design with Verilog HDL
Hierarchical Modeling Concepts
Basic Concepts
Modules and Ports
Gate-Level Modeling
Dataflow Modeling
Behavioral Modeling
Tasks and Functions
Useful Modeling Techniques

PART-II ADVANCED VERILOG TOPICS

Timing and Delays
Switch-Level Modeling
User-Defined Primitives
Programming Language Interface
Logic Synthesis with Verilog HDL

PART-III APPENDICES

Strength Modeling and Advanced Net Definitions
List of PLI Routines
List of Keywords, System Tasks, and Compiler Directives
Formal Syntax Definition
Verilog Tidbits
Verilog Examples


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Product Details
  • ISBN-13: 9788178084893
  • Publisher: Pearson Education
  • Binding: Paperback
  • ISBN-10: 8178084899
  • Publisher Date: 1996
  • Language: English

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