1 Introduction.
2 Fundamentals of Non-Volatile Memories. 2.2 Non-Volatile Storage Element - Cell Operation Modes. 2.3 Non-Volatile Cell - Electron and Non-Electron based. 2.4 Flash Memory Array. 2.5 Memory Building Blocks. 2.6 Flash Memory Algorithm and Vth Window Definition. 2.7 Multiple Bits per Cell Area - Flash Memory Concepts. 2.8 Summary of NVM Fundamentals.
3 Performance Figures of Non-Volatile Memories. 3.1 Memory Performance Parameter Definition. 3.2 Performance Parameters for Flash Memories. 3.3 Performance and Durability. 3.4 Performance Parameter and Durability Summary.
4 Fundamentals of Reliability for Flash Memories. 4.1 Reliability Parameter based on Vth Window Margin Analysis. 4.2 Data Integrity - Data Retention Parameter. 4.3 Reliability Parameter Endurance - Number of Writes. 4.4 4.5 Reliability Margin Optimization on Product Level. 4.6 Flash Memory Reliability Summary.
5 Memory based System Development and Optimization. 5.1 5.2 Memory-Centric System Specification. 5.3 Memory Efficiency Parameters for Competitiveness. 5.4 Memory System Optimization. 5.5 Summary - Flash Memory based System Optimization.
6 Memory Optimization - Key Performance Indicator Methodology. 6.1 Performance, Cost per bit, and Reliability Optimization. 6.2 Definition of Performance Indicators. 6.3 Definition of a Performance Indicator Model . 6.4 Application of Performance Indicator Methodology. 6.5 Performance Indicator Methodology Summary.
7 System Optimization based on Performance Indicator Models. 7.1 7.2 Economic Principles of memory-centric System Development. 7.3 System Optimization based on Memory Array differences. 7.4 Integral Memory-centric System Optimization. 7.5 Failure Tolerant Systems - Design for Durability.
8 Conclusion and Outlook. 8.1 8.2 Summary. 8.3 Outlook for Flash Memories.
9 References.
Recent Publications by the Author.
About the Author: Detlev Richter is Business Area Manager at TÜV SÜD Automotive GmbH in Garching, Germany responsible for powertrain technologies. Before he led the electronic development for power inverters at Semikron GmbH & Co. KG in Nuremberg.
Before he was Director at Qimonda Flash GmbH, where he led the Product Innovation for flash memoires based on multi-bit charge trapping and multi-level floating gate flash cells. Before he was Director at Infineon Technologies AG, where he led the Product Engineering and Test activities for flash memories, ASIC's, SOC with embedded DRAM and speciality DRAM. His research interests include "fault analysis of memories based on defect injection and simulation", "Innovative cell and sense concepts for non-volatile memories" and "Enhancement of MLC Flash using improved ECC techniques".
Before he was product engineer responsible for process integration and optimization for bipolar power technologies at BOSCH in Reutlingen.
He studied Electrical Engineering at TU Sofia and TU Dresden and has the Dipl.-Ing. Degree from the Technical University of Dresden.
