Home > Society & social sciences > Education > Educational equipment & technology, computer-aided learning (cal) > Etude d'attaques matérielles et combinées sur les System-on-Chip: Thèse pour obtenir le grade de docteur de l'Université Jean Monnet
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Etude d'attaques matérielles et combinées sur les System-on-Chip: Thèse pour obtenir le grade de docteur de l'Université Jean Monnet

Etude d'attaques matérielles et combinées sur les System-on-Chip: Thèse pour obtenir le grade de docteur de l'Université Jean Monnet

          
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About the Book

Jusqu'à présent, les applications nécessitant un haut niveau de sécurité (paiement, communications, identification, etc.) utilisaient des systèmes exclusivement dédiés tels que les cartes à puce qui intègrent une multitude de contre-mesures logicielles et physiques. Avec la démocratisation des smartphones et autres objets connectés, la manipulation des données sensibles tend à être déléguée à des systèmes plus complexes communément appelés systèmes sur puce, ou en anglais "Systems on Chip" (SoC). L'intérêt de la communauté de la sécurité numérique dans ce domaine s'est essentiellement focalisé sur les menaces logicielles, améliorant sans cesse le niveau de protection. Cependant, l'exploitation de ce vecteur d'attaque devenant de plus en plus difficile, il est fort probable que les attaques matérielles se multiplient. Par conséquent, il est primordial d'étudier ces dernières afin d'anticiper la menace qu'elles représentent. La sophistication de l'architecture et la rapidité d'évolution des technologies embarquées dans les SoC, justifient la mise en place d'une méthodologie adaptée pour évaluer efficacement leur niveau de sécurité. C'est dans ce contexte que le travail présenté dans cette thèse propose l'étude de la faisabilité de cette catégorie d'attaques ainsi qu'un aperçu de leur impact sur la sécurité de ce type de systèmes. Alors que les architectures élaborées accroissent la difficulté de mise en place d'attaques physiques, elles augmentent également la surface d'attaque. Une première étude analyse les chemins d'attaques afin de déterminer les grandeurs physiques exploitables les plus pertinentes. Cette étape conduit, dans un deuxième temps, à l'élaboration de règles génériques pour l'évaluation sécuritaire des SoC présents sur le marché. Celles-ci combinent diverses techniques en partie déjà utilisées dans le domaine de la carte à puce. L'ensemble de ce travail s'appuie sur plusieurs cas d'études relatifs à divers modules caractéristiques de la sécurité des systèmes sur puce actuels. Tous les résultats observés aboutissent aux mêmes constatations: la complexité inhérente aux SoC n'est pas suffisante pour les protéger contre les attaques matérielles et l'implémentation des sécurités dans ces systèmes doit se faire sans se reposer sur cette propriété.


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Product Details
  • ISBN-13: 9781729496121
  • Publisher: Independently Published
  • Publisher Imprint: Independently Published
  • Height: 279 mm
  • No of Pages: 336
  • Spine Width: 22 mm
  • Weight: 1078 gr
  • ISBN-10: 1729496121
  • Publisher Date: 17 Dec 2018
  • Binding: Paperback
  • Language: French
  • Returnable: N
  • Sub Title: Thèse pour obtenir le grade de docteur de l'Université Jean Monnet
  • Width: 216 mm


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