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Analyse comparative du traitement séquentiel et du traitement simultané pour les flottants

Analyse comparative du traitement séquentiel et du traitement simultané pour les flottants

          
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About the Book

Les additionneurs à virgule flottante sont difficiles à mettre en oeuvre sur des dispositifs reconfigurables en raison de la complexité de leur algorithme. Le travail proposé décrit la mise en oeuvre d'un additionneur à virgule flottante utilisant un traitement séquentiel et concurrent sur du matériel reconfigurable. La mise en oeuvre de l'additionneur à virgule flottante à l'aide du traitement séquentiel utilise moins de surface de puce, mais avec une augmentation significative du retard combinatoire et de la période d'horloge par rapport au traitement simultané. La mise en oeuvre de l'additionneur à virgule flottante par traitement simultané sur Virtex 4 consomme 7 % de la surface de la puce avec un retard combinatoire de 24,201 ns sans décalage et de 27,891 ns avec décalage, et la mise en oeuvre de l'additionneur à virgule flottante sur Spartan 2E par traitement simultané utilise 401 tranches avec un retard combinatoire de 56,679 ns et consomme 188 ns. 679nsec et consomme 188908 Kbytes de mémoire alors que l'implémentation sur Spartan 2E en utilisant le traitement séquentiel consomme 52% de la surface de la puce avec un délai combinatoire de 69.987nsec et cela implique que la vitesse d'horloge du traitement concurrent est plus élevée que le traitement séquentiel mais que la consommation de surface est également plus élevée.


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Product Details
  • ISBN-13: 9786207349166
  • Publisher: KS Omniscriptum Publishing
  • Publisher Imprint: Editions Notre Savoir
  • Height: 229 mm
  • No of Pages: 68
  • Spine Width: 4 mm
  • Width: 152 mm
  • ISBN-10: 6207349164
  • Publisher Date: 03 Apr 2024
  • Binding: Paperback
  • Language: French
  • Returnable: N
  • Weight: 113 gr


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Analyse comparative du traitement séquentiel et du traitement simultané pour les flottants
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