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Analisi comparativa dell'elaborazione sequenziale e concorrente per i galleggianti

Analisi comparativa dell'elaborazione sequenziale e concorrente per i galleggianti

          
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About the Book

Gli addizionatori in virgola mobile sono difficili da implementare su dispositivi riconfigurabili a causa della complessità del loro algoritmo. Il lavoro proposto descrive l'implementazione di un sommatore in virgola mobile con elaborazione sequenziale e concorrente su hardware riconfigurabile. L'implementazione di un sommatore a virgola mobile con elaborazione sequenziale utilizza una minore area del chip, ma con un aumento significativo del ritardo combinazionale e del periodo di clock rispetto all'elaborazione concorrente. L'implementazione dell'addizionatore in virgola mobile con l'elaborazione concorrente su Virtex 4 consuma il 7% dell'area del chip con un ritardo combinazionale di 24,201nsec senza offset e 27,891nsec con offset, mentre l'implementazione dell'addizionatore in virgola mobile su Spartan 2E con l'elaborazione concorrente utilizza 401 slice con un ritardo combinazionale di 56,679nsec e consuma 188 slice. 679nsec e consuma 188908 Kbyte di memoria, mentre l'implementazione dello stesso su Spartan 2E con l'elaborazione sequenziale consuma il 52% dell'area del chip con un ritardo combinazionale di 69,987nsec; ciò implica che la velocità di clock dell'elaborazione concorrente è superiore a quella dell'elaborazione sequenziale, ma anche il consumo di area è maggiore.


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Product Details
  • ISBN-13: 9786207349173
  • Publisher: KS Omniscriptum Publishing
  • Publisher Imprint: Edizioni Sapienza
  • Height: 229 mm
  • No of Pages: 68
  • Spine Width: 4 mm
  • Width: 152 mm
  • ISBN-10: 6207349172
  • Publisher Date: 03 Apr 2024
  • Binding: Paperback
  • Language: Italian
  • Returnable: N
  • Weight: 113 gr


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Analisi comparativa dell'elaborazione sequenziale e concorrente per i galleggianti
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